Forum Index : Electronics : Various aspects of home brew inverters

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ltopower
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Joined: 08/03/2019
Location: United Kingdom
Posts: 64

Posted: 11:20pm 24 Mar 2019

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'But I am still not absolutely certain in my own mind exactly HOW it works.' Glad its not just me...
Another set of really interesting charts...
In the original W7 modification Andrew added a 820mH choke on the output with a smaller cap as an 8kHz filter to block any connected loads feeding back changes to the resonances within the inverter. This should also help smooth out some of the distortions.
High 'Crest Factor' load is shown really nicely for the Mac Book power supply... UPS units define the crest factor capability in the specifications, typically they can handle around 3.
The UPS profile looks like a harmonic is causing the spikes with the spacing ? As I understand the smaller UPS units they are typically HF, which should not cause spikes like what you are seeing in the charts.
Would be really interesting to see the UPS connected up with an inline LC for 8kHz in place (820mH and 0.47uF)...

poida
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Joined: 02/02/2017
Location: Australia
Posts: 998

Posted: 03:16am 25 Mar 2019

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Part 30: MOSFET gate voltages with Madness's power board
Now the nanoverter is running well, I have found it useful for looking at
potential causes of failure with our inverters.
This time I am looking at the dv/dt induced voltage changes at MOSFET gate pins
and the voltages seen at the IR21844 gate drive IC outputs.
I have been very wary of negative voltages appearing on the drive IC outputs.
I suspect these -ve voltages have resulted in inverter failures.
I have no proof, mind, but IR specify Absolute maximum rating for Vlo
as from -0.3V to (Vcc+0.3V).
I have seen Vlo voltages much less than -0.3V in other inverters I tested on the bench.
This has lead me to use and recommend 15V TVS diodes across Vlo to ground and
Vho to Vs (high side gate drive and VS).
Now the Madness power board is built, let's see what voltages appear on the gate drive outputs, now they only need to drive the two transistor base pins, thanks to Madness choosing a on-board totem pole gate drive design.
(yet more DSO screens follow)
Light Blue is IR21844 gate drive output, sampled very close to the IC pins.
Pink is MOSFET gate voltage
Firstly, no load condition.
Close to the beginning of a 1/2 wave:
Notice the MOSFET gate exhibits large voltage spikes due to dv/dt (i.e. fast voltage changes at VS)
These spikes do not find their way back to the gate drive IC outputs.
Nice.
Now at the other end of the 1/2 wave:
Again, the negative pulse was not seen at the gate drive IC.
Something else to see, there is indication of oscillation when the low side MOSFETS switch ON, to pull VS to ground. This oscillation is also not present on the gate drive IC outputs.
Now, with 150W load, we see near the start:
A lot more changes on the gate voltage at the MOSFET.
Look at the huge negative spike just before MOSFET switch ON.
That was completely insulated from the drive IC pin. None of it got through.
We can see more energetic oscillations now, with a bit of load on the bridge.
And near the end of the half wave, under load:
pretty much the same.
I have to conclude that totem-pole MOSFET drive has shown the best, least potentially destructive gate drive voltages on the IR21844 drive chips.
This seems to me to be the way to go in power board design.
Wiseguy has a project using potentially better performing gate drive, made with optocouplers and isolated DC supplies, etc. I look forward to seeing how his design works too.
I think the inverters we have built, using the outputs from the IR2110, direct into MOSFET gates, via a 5R resistor (or something) bring some issues of reliability
thanks to the dv/dt voltage pulses that can damage the gate drive ICs.
My idea of using 15V TVS diodes is a bandaid. It works.
But I think to avoid conveying damaging voltages back to the drive ICs would be the better approach to take by using totem pole drives located close to the MOSFETS.
Totem-pole drive:
This is a small clip of Tinker's schematic.
The gate drive IC output is fed into the bases of the two transistors via the 22R resistor. If the current is high enough, one transistor will conduct. If the current is low enough, the other transistor will keep conducting. Both won't be conducting for very long. Voltages appearing on their emitters and collectors won't get back to their base pins, as we have seen in the above DSO traces.
this is how the testing was done:
Looking at the traces again, I see the gate drive IC outputs exceeding 15V, maybe getting to 16.5V. This is not good, I know the IC's have a supply of 15V.
The specs say no more than DC supply + 0.3V
I think we need the TVS or 15V zener diodes after all!
I will put them across the point where the two transistor bases join, and to ground or VS where appropriate. Edited by poida 2019-03-26wronger than a phone book full of wrong phone numbers

Warpspeed
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Joined: 09/08/2007
Location: Australia
Posts: 4010

Posted: 03:40am 25 Mar 2019

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My understanding of this negative transient on the gate driver problem, is that there are two very different integrated circuit technologies.
A great many of the switching power supply control chips have outputs capable of driving large mosfet gate capacitances. These chips also have a lot of internal analog circuitry such as op amps, voltage references, and so on. Most if not all use bipolar transistors throught, including the gate driver output stage that provides the high current drive output.
If you read the application notes, they specifically warn about negative voltages on the output causing catastrophic latch up, and destruction of the chip, and they often recommend connecting really enormous Shottky diodes down to ground to block these negative transients.
The other type of mosfet gate driver chips you will see are all CMOS technology, and use large mosfets in the high power output stage. These chips have mostly all digital circuitry internally.
Anyhow, the two large mosfets on the output have the usual drain/souce diodes that effectively clamp any transients and so the latchup problem does not exist.
So it might be a really big problem with bipolar chips, or it might be no problem at all with CMOS chips.
Just look up the data sheet for whatever drives your mosfet gates, and read the application notes. Then you will know for sure.
All the International Rectifier IR21xx devices are CMOS so there are no worries about ringing or transients punching back into the driver with destructive negative (or positive) transients.
All the dedicated high power gate driver chips like TC4452 are o/k too, as are the opto isolated gate drivers like HCPL3120.
Its only the complex PWM switch mode control chips that have a lot of analog c

Totem Pole Mosfet Driver For Mac